Scan-based testing has proven to be a cost-effective method to achieve good test coverage in digital circuits, and hence has been widely adopted in most designs. Traditionally, if a circuit fails a test, physical failure analysis (PFA) and yield learning techniques are used to locate root causes of the failure. However, advances in semiconductor technologies and increasing complexity of designs are rendering this approach inadequate. Scan-based diagnosis can help to guide PFA to focus on chip areas where defects are likely to be found and thus speedup yield ramp-up processes.
Scan-based diagnosis techniques can be divided into three categories: system logic diagnosis, scan chain diagnosis, and compound fault diagnosis. The system logic diagnosis assumes that defects reside in the circuit under test while scan chains work correctly. The scan chain diagnosis, on the other hand, assumes only scan chains may be problematic. As its name indicates, the compound fault diagnosis tries to locate defect suspects in both scan chains and the circuit under test.
All the three categories of scan-based diagnosis techniques have developed various hold-time fault models. In the system logic diagnosis, the hold-time fault models have been built around source scan cells, sink scan cells, the paths connecting the source and sink scan cells, or clock trees. These fault models are not suitable for either scan chain hold-time fault diagnosis or compound hold-time fault diagnosis. Some of the scan chain hold-time diagnosis techniques may locate the scan cell(s) that suffer hold-time fault(s) during scan chain shift. However, they cannot discern whether the real root cause is on the scan chain or clock. While some other of the scan chain hold-time diagnosis techniques may diagnose scan chain stuck-at faults caused by clock defects, they cannot be applied directly to diagnose slow clock faults. It has been found that compound hold-time faults are often caused by defects is in the global control signals such as the clock signals. These defects cannot be located by simply running any conventional compound fault diagnosis procedures.